patch-2.2.11 linux/arch/sparc64/kernel/psycho.c

• Lines: 55
• Date: Mon Aug 9 12:05:45 1999
• Orig file: v2.2.10/linux/arch/sparc64/kernel/psycho.c
• Orig date: Thu Apr 22 19:24:51 1999

diff -u --recursive --new-file v2.2.10/linux/arch/sparc64/kernel/psycho.c linux/arch/sparc64/kernel/psycho.c
@@ -1,4 +1,4 @@
-/* $Id: psycho.c,v 1.85 1999/04/02 14:54:28 davem Exp $
+/* $Id: psycho.c,v 1.85.2.2 1999/08/09 13:00:21 davem Exp $
  * psycho.c: Ultra/AX U2P PCI controller support.
  *
  * Copyright (C) 1997 David S. Miller (davem@caipfs.rutgers.edu)
@@ -756,14 +756,16 @@
 	struct pci_dev *pdev;
 	unsigned short stmp;
 	unsigned int itmp;
+	unsigned char btmp;
 
 	for(pdev = pci_devices; pdev; pdev = pdev->next) {
 		if(pdev->vendor == PCI_VENDOR_ID_SUN &&
 		   pdev->device == PCI_DEVICE_ID_SUN_SABRE) {
-			pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 128);
+			pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 64);
 			break;
 		}
 	}
+
 	for (pdev = sabre->pci_bus->devices; pdev; pdev = pdev->sibling) {
 		if (pdev->vendor == PCI_VENDOR_ID_SUN &&
 		    pdev->device == PCI_DEVICE_ID_SUN_SIMBA) {
@@ -800,8 +802,28 @@
 			 * timer settings.  But do set primary and secondary
 			 * latency timers.
 			 */
-			pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 128);
-			pci_write_config_byte(pdev, PCI_SEC_LATENCY_TIMER, 128);
+			pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 64);
+			pci_write_config_byte(pdev, PCI_SEC_LATENCY_TIMER, 64);
+
+			/* Here is an overview of the behavior of various
+			 * revisions of APB wrt. write buffer full conditions:
+			 *
+			 * Revision 1.0: pre-FCS, always stalls
+			 * Revision 1.1: pre-FCS, always disconnects
+			 * Revision 1.2: same behavior as rev 1.1
+			 * Revision 1.3: behavior is determined by bit 4 of
+			 *               secondary control register
+			 *		 0: stall initially, but disconnect
+			 *		    if PCI latency timer expires
+			 *		 1: always disconnect
+			 *
+			 * By setting the bit, since it is reserved in previous
+			 * revisions of APB, we get all FCS hardware to have
+			 * identical behavior when APB's write buffer fills up.
+			 */
+			pci_read_config_byte(pdev, APB_SECONDARY_CONTROL, &btmp);
+			btmp |= APB_SECONDARY_CTL_DISCON_FULL;
+			pci_write_config_byte(pdev, APB_SECONDARY_CONTROL, btmp);
 		}
 	}
 }