Click model number for photo


3341 8-INPUT SPECTROSCOPY GRADE CHARGE INTEGRATING ADC

3351 8-INPUT SPECTROSCOPY GRADE PEAK SENSING ADC

3371 8-INPUT SPECTROSCOPY GRADE TDC

FOR HIGH RESOLUTION CHARGE, VOLTAGE AND TIME MEASUREMENTS


The LeCroy Model 3341 Charge Analog-to-Digital Converter, Model 3351 Peak Sensing Analog-to-Digital Converter and the Model 3371 Time-to-Digital Converter each have 8 channels of high resolution, data acquisi tion. These modules are compatible with LeCroy FERA and ECLbus systems.

The modules are highly stable, offering superior integral and differential linearity performance, as well as fast con version and readout capabilities.

The Models 3341, 3351 and 3371 have been designed for use in a variety of experimental situations that employ many ADC or TDC channels to perform high resolution, high stability data acquisition.

FUNCTIONAL DESCRIPTION

The Model 3341 is an 8-channel charge integrating analog-to-digital converter. The charge of each individual input current pulse which occurs within a given gate interval is collected and digitized by the 3341. The gate interval duration may range from 20 nsec to 2 µsec (10 µsec on request), and is controlled by the duration of a gate command pulse, which is common to the 8 channels of the module. The circuit can work on signal sources of any impedance level, from the high values of PMT anode outputs to the low values of preamplifier outputs.

The 3341 also features DC baseline cancellation, true differential inputs, and low noise.

The circuit can work with any desired input impedance. The standard value is 50 ohm input for coaxial cable connections, but other arrangements may be supplied (i.e., 100 ohm input suitable for twisted pair connections). The circuit has been designed and tested for performance at a level suitable for high resolution spectroscopy.

In addition, the 3341 has an auxiliary discriminator which can be set automatically. The discriminator itself gener ates a gate signal for the ADC.

The Model 3351 has 8 input channels which acquire the peak voltage of the input signals that occur within the time interval marked by a common gate signal. The circuit accepts all the typical pulse shapes of nuclear elec tronic modules, such as spectroscopy amplifiers, time-to-amplitude converters.

The Model 3371 is an 8-channel Common Start Time-to-Digital converter. It has a full scale of 200 nsec with a least count of 50 psec. This module includes an upper level and lower level discriminator for time window mea surements.

For all modules, digitized data are available first on the front-panel ECL port and then on the CAMAC dataway, giving the user two readout options. All zero or zero-and-overflow data words may be suppressed to provide data compression.

The front-panel bus system includes the protocol necessary to allow high speed sequential readout to the LeCroy series of ECLine Data Handler Modules and to the Model 4302, Dual Port Fast Memory. The same bus can provide interfacing and data storage in FASTBUS where data can be received by the Model 1892, FASTBUS Memory, or in VME to Memory Model 1190 (request application notes AN-4001, AN-4004A and AN-39, and publication P-2 for examples).

SPECIFICATIONS

Model 3341 Charge ADC


Analog Inputs: 8. Negative pulses, any source impedance. The linear operating range does not depend on the DC baseline level (within the above specified range) but only on the pulse peak value: maximum pulse-peak value -1 V (i.e., -10 mA on 100 ohm). Extended linear range available by reducing the input sensitivity and the corre spondingly higher full scale value in the charge measurement. Minimum pulse detectable by the circuit providing the DC cancellation: 2 mV with normal input linear range 0.2% of full scale value with extended input voltage range.

Connector: 10x2-pin front-panel connector (ANSLEY 609-2007). The upper 8 pins of the left row are negative input signals. The upper 8 pins of the right row are signal returns. The last 2+2 pins are connected to ground (may be used to connect the twisted pair shield to ground).

Type: True differential, suited to work with negative signals and positive and negative baseline and common mode noise and interferences. Single-ended internally selectable by jumper.

Coupling: DC.

Impedance: 50 ohm standard; other values available on request.

Signal Baseline: The DC level of the input signal baseline may have any value in the ±0.2 V range (i.e., ±5 mA on 100 ohm), as the circuit provides internal cancellation of the DC level within this range.

Common Mode Range: ±0.5 V.

Common Mode Rejection: CMRR > 80 dB from DC to 100 Hz. CMRR > 60 dB from 100 Hz to 50 kHz.

System Noise as a Function of Gate Width:

10 nsec to 0.5 µsec - not detectable.
1 µsec is -0.09 pC FWHM
2 µsec is -0.12 pC FWHM
5 µsec is -0.3 pC FWHM
10 µsec is -0.6 pC FWHM

Input Protection: ±25 V from 1 µsec transients (clamping DIODES from GND and -3 V).

Crosstalk: 66 dB.


DC Input Cancellation


Type: Circuit measuring the mean level of the input baseline and feeding back an opposite continuous level. Exclusion of contributions to the measured mean level from intervals occupied by input pulses sensed by the auxiliary threshold or marked by signals applied to the "hold" input.

Count Rate Shift: Not detectable up to 150 kHz.

Auxiliary Threshold Setting: Under CAMAC control, (8-bit resolution) common to the 8 input channels of the module.

E Input Lemo Connector: As a logic signal is applied, the measurement of the mean input level is suspended and the cancelling level feed back is held constant for the duration of the logical signal. The maximum allowed duty cycle of the "hold" logical signal is 50%, with duration of the time intervals between adjacent "hold" signals of at least 100 µsec.

Integrator


Linear Range: Normal 0 to 256 pC, referred to input current signals on 100 ohm. Extended range available with correspondingly reduced input sensitivity, on request.

Integral Linearity: Typically ±0.025% of full scale, better than ±0.05%; in any case over 95% of the dynamic range.

Differential Linearity: Typically ±0.5% better than ±1%; in any case over 95% of the dynamic range.

Temperature Dependence: Typically ±0.005% of full scale value/°C, i.e., ±12.5 fC/°C for the normal range, independent of the gate width.

Conversion Gain: Typically ±100 ppm/°C independent of the gate width.

ADC


Resolution: 3840 channels (4096 minus 256 channels for sliding scale), corresponding to 62.5 fC/channel in the normal integration range.

Conversion Time: 3 µsec for every valid input channel.

System Busy Time with Zero Suppression:
Variable as a function of the number of valid channels.
Valid Channel: 4 µsec.
Channel Without Signal ln or Outside the Preselected Window (LLD-ULD): 1.1 µsec.
Total Busy Time: BTCh 1 + BTCh 2 + ... BT Ch 8 + 1 µsec.

System Busy Time without Zero Suppression: Fixed 33 µsec.

DC Offset Control: ±3% of full scale value, CAMAC control 8 bits.

Selection of Acceptable Analog Inputs: By means of separate lower and upper level discriminators for each channel under CAMAC control with 8-bit resolution. LLD from 0 to 10% of dynamic range. ULD from 100 to 85% of dynamic range.

Model 3351 Peak Sensing ADC


Analog lnputs: 8; 100 mV to 10 V.

Connector: 8x2-pin front panel connector (Ansley 609-1607). The 8 pins of the left row are positive signal inputs; the 8 pins of the right row are ground returns.

lnput Sensing: Peak voltage.

Coupling: DC.

lmpedance: 1 kohm; other values available on request.

Signal Polarity: Positive.

Signal Shape: All typical shapes from nuclear electronic modules, such as semi gaussian, RC-RC shaped, quasi rectangular are accepted, provided that the pulse peaking time t pk (defined as the time from the onset of the pulse to the point where the pulse reaches its maximum height) is within the range. 8 µsec t pk 1 µsec.

Selection of Acceptable Analog Inputs: By means of the common threshold level for all channels for noise rejection under CAMAC control with 8-bit resolution (0 to 1 Volt) and separate lower and upper level discrimina tors for each channel under CAMAC control with 8-bit resolution (LLD from 0 to 10%, ULD from 100% to 85%).

Resolution: 3840 channels (4096 minus 256 channels for sliding scale) corresponding to 2.5 mV/ch.

Conversion Time: 3 µsec for every valid input channel.

System Busy Time with Zero Suppression:
Variable as a function of the number of valid channels.
Valid Channel: 4 µsec.
Channel Without Signal-ln: 0.23 µsec.
Channel With Signal ln but Outside the Preselected Window (LLD-ULD): 1.1 µsec.
Total Busy Time: BTCh 1 + BTCh 2 + ... BT Ch 8 + 1 µsec.

System Busy Time without Zero Suppression: Fixed 33 µsec.

DC Offset Control (Zero Energy Intercept): ±3% of full scale value under CAMAC control with 8-bit resolution.

Integral Linearity: Typically ±0.025% of F.S., better than 0.05%; in any case over 95% of the dynamic range. Measured with 0.5 µsec semi-gaussian pulse shape. (t pk = 1.2 µsec).

Differential Linearity: Typically ±0.5%, better than ±1%, in any case over 95% of the dynamic range.

Gain Stability: 100 ppm/°C.

Zero Stability: 200 µV/°C.

Cross Talk Between two Adjacent Inputs: > 66 db (measured with 0.5 µsec semi-gaussian pulse shape).

Count Rate Shift: Not detectable at 100 kHz.

Model 3371 TDC


Stop lnputs: 8; ECL differential.

Connector: 8x2-pin front-panel connector (Ansley 609-1607). The 8 pins of the left row are positive signal inputs; the 8 pins of the right row are negative signal inputs.

Impedance: 100 ohm differential (50 ohm single-ended on request).

Minimum Width: 10 nsec.

Full Scale Time Range: Normal 200 nsec, corresponding to 50 psec per ADC level. Other values available on request, from 200 nsec to a maximum of 10 µsec.

ADC Resolution: 12 bits.

Integral Linearity: Typically ±0.05% of F.S., better than 0.1% F.S. (measured from channel 200 and 200 nsec of F.S. time range. Higher F.S. time ranges improve proportionally non linearity up to full dynamic).

Differential Linearity: Typically ±0.5%, better than 1%. (Measured from channel 200 and 200 nsec of F.S. time range. Higher F.S. time ranges improve proportionally non linearity up to full dynamic).

Conversion Time: 3 µsec for every valid input channel.

System Busy Time with Zero Suppression: Variable as a function of the number of valid channels.
Valid Channel: 4 µsec.
Channel Without Stop Pulse or Outside the Time Window (LLD-ULD): 1.1 µsec.
Total Busy Time: BTCh 1 + BTCh 2 + ... BT Ch 8 + 1 µsec.

System Busy Time Without Zero Suppression: Fixed 33 µsec.

Time Window: Selected by means of separate lower and upper level discriminators, under CAMAC control with 8-bit resolution (LLD from 0 to 10%; ULD from 100% to 85%).

DC Offset Control: ±3% of full scale value, under CAMAC control with 8-bit resolution.

Cross Talk Between Two Adjacent Inputs: Maximum ±10% of channel width (±5 psec measured with F.S, time range of 200 nsec).

Full Scale Stability: ±100 ppm/°C.

Zero Stability: ±100 ppm/°C of full scale.

STATUS WORD REGISTER FORMAT

R1-R8 (VSN): Logical address of module: index source for sequential readout with zero suppression.

R10 (SUB): Channel Subaddress Enable (enabled when SUB = 0).

R11 (EEN): ECL Readout Enable. EEN = 1 ECL Readout. EEN = 0 CAMAC Readout.

R12 (OVF): Overflow indication Enable (enabled when OVF = 0).

R13 (CCE): Acquisition and Readout Control.

R14 (CSR):

- With zero suppression (sequential readout) CSR = 1 and CCE = 1.
- Without zero suppression (sequential readout) CSR = 1 and CCE = 0.
- Addressed readout (without zero suppression) CSR = 0 and CCE = X.

R15 (CLE): CAMAC LAM Enable (enabled when CLE = 1).

Command Bus


Connector: 8x2-pin front-panel connector. The input matching resistors and output pull-down resistors may be removed to achieve high input and output impedances. When these resistors are mounted, the associated LED indicator (PD ON) is illuminated.

Input Level: Differential ECL.

Impedance: 100 ohm differential.

Output Level: Differential ECL (into 100 ohm differential).

Gate Input (GTE):
Gate Width: 20 nsec to 2 µsec standard, 10 µsec optional.

Clear Input: Common for all analog and digital logic. Pulse width 50 nsec. The module is ready to process a new event after 1.2 µsec.

Request Output (REQ): Indicates that the module is ready to send data to the ECL DATA BUS. The REQ signal is generated at the end of conversion if the bit related to ECL READOUT in the Status Register has been set.

Write Strobe Output (WST): Indicates the time period during which the data present in the ECL Data bus can be stored in the external memory. WST is generated in a minimum of 10 nsec after the data is ready. Its width is higher than 40 nsec. During the entire WST pulse, the ECL Data Bus data is maintained stable.

Write Acknowledge Input (WAK): This input receives the acknowledge signal indicating that the data present on the ECL bus has been loaded into memory and the next data word may be sent. The next WST signal is generated at least 50 nsec after the WAK signal. Minimum WAK width must be 30 nsec.

Busy Output (BSY): This output is set to the "1" state 1 µsec after the end of the GATE signal and is held to this state until after the end of the readout cycle (ECL Readout or CAMAC Readout). The BUSY state may be reset only by sending a CLEAR signal via CAMAC or via ECL BUS (CLR). The ADC is ready to start a new conversion 1.2 µsec after the end of the BUSY state.

ECL PORT ENABLE/PASS


Readout Enable Input (REN): 1x2-pin panel connector. The REN signal indicates to the module that it can take control of the ECL Data Bus; REN must be maintained during the entire readout time. The signal enables the ECL Data Bus, WST Output and WAK input if the module is ready for data transfer (REQ output ON).

Input Level: Differential ECL.

Input Impedance: 100 ohm differential.

Pass Output (PAS): 1x2-pin front-panel connector. Indicates that the module is not ready to transfer data present on the ECL Data Bus or it has finished data transfer. The PASS output signal is generated by the REN line in the absence of the REQ internal command or, if this command is present, at the end of data readout. The transit time between REN and PASS output is typically 3 nsec if the module does not include data readout capabilities.

Output Level: ECL differential (into 100 ohm differential).

ECL PORT OUTPUT


Connector: 17x2-pin front-panel connector (ANSLEY 609-3407). The last two pins are not connected.

Output Level: Differential ECL level (into 100 ohm differential). The pull-down resistors must be removed for high impedance outputs. When these resistors are mounted, the associated LED indicator (PD ON) is illumi nated.

Data Word Size: 16 bits.

Readout Mode: Sequential.

Max Readout Frequency: 8 MHz.

CAMAC COMMANDS

CAMAC COMMANDS


Z: Initialize; clears the module and the Status Register.

C: Clears the module; does not clear the Status Register and Memory.

I: Inhibits the front-panel GATE during CAMAC inhibit command.

X: X response is generated for all valid functions.

Q: Q response is generated when the function can be executed.

L: LAM (Look-at-Me) is set after the end of conversion, if it was enabled, with CAMAC Readout enabled.

CAMAC FUNCTION CODES


F(0)·A(0) or F(2)·A(0): Reads Data: a) With zero suppression (CSR = 1 CCE = 1). b) Without zero suppression (CSR = 1 CCE = 0).
Note: CSR and CCE are Status Word Bits (see Status Word).

F(0)·A(0-7) or F(2)·A(0-7): Reads Data: Addressed readout (CSR = 0 CCE = X).

F(0)·A(14) or F(2)·A(14): Reads Header Word.

F(0)·A(15): Reads Pattern Word.

F(2)·A(15): Reads Pattern Word and clears LAM.

F(1)·A(0-7): Reads Threshold Memory (Upper Threshold - ULD).

F(1)·A(8-15): Reads Threshold Memory (Lower Threshold - LLD).

F(4)·A(0-7): Reads Offset Memory.

F(4)·A(9): Reads Common Threshold.

F(4)·A(14): Reads Status Word Register.

Click here for chart

F8·A(0): Tests LAM. Q = 1 if LAM is present.

F9·A(0): Clears the Module.

F10·A(0): Clears LAM and Clears Single Channel Mode.

F16·A(0-7): Single Channel mode (Autotrigger). For 3341 only.

F17·A(0-7): Writes Threshold Memory (Upper Threshold - ULD).

F17·A(8-15): Writes Threshold Memory (Lower Threshold - LLD).

F20·A(0-7): Writes Offset Memory.

F20·A(9): Writes Common Threshold. For 3341 and 3351 only.

F20·A(14): Writes Status Word.

F25·A(0): Test Function.

READOUT FORMAT

Note: EEN, CSR and CCE are Status Word bits (see Status Word).

1) With zero suppression (sequential readout):

CSR = 1 CCE = 1
EEN = 1 ECL Port Readout
EEN = 0 CAMAC Readout

Click here for diagram

VSN: Virtual Station Number; loaded in the associated Memory.

VDC: Number of Valid Data following Pattern Word (from 1 to 8).

PW: Valid Data View: R1 is referred to Channel 0; R8 is referred to Channel 7.

OVF: Overflow Indication; enabled with OVF = 0 (Status Word bit).

SUB: Channel Subaddress, enabled with SUB = 0 (Status Word bit).

DATA: 12-bit Output Data.

There is sequential readout. CAMAC Readout function F(0)·A(0) or F(2)·A(0).

2) Without zero suppression (sequential readout):

CSR = 1 CCE = 0
EEN = 1 ECL Port Readout
EEN = 0 CAMAC Readout

There is always sequential readout of 8 words.

OVF: Overflow Indication; enabled with OVF = 0 (Status Word bit).

SUB: Channel Subaddress, enabled with SUB = 0 (Status Word bit).

Click here for diagram

3) CAMAC Addressed Readout:

CSR = 0 CCE = Indifferent
EEN = 0 Only CAMAC Readout

There is CAMAC Addressed Readout with F(0)·A(0-7) or F(2)·A(0-7) functions. F(2)·A(7) clears the module during S2. Header can be read out with F(0)·A(14) or F(2)·A(14).

Pattern Word can be readout with F(0)·A(15) or F(2)·A(15).

OVF: Overflow Indication; enabled with OVF = 0 (Status Word bit).

SUB: Channel Subaddress, enabled with SUB = 0 (Status Word bit).

Click here for diagram

Simplified block diagram of the Models 3341, 3351 and 3371. Note - shaded area included in the ADC modules only.


General


Packaging: RF-shielding 1-width CAMAC module.

Power Requirements: Click here for Table

Note: When all output pull-down and input matching resistors are removed, the current at -6 V is reduced to:

3341: 1.85 A
3351: 1.4 A
3371: 1.45 A

Copyright© December 1995. LeCroy is a registered trademark of LeCroy Corporation. All rights reserved. Information in this publicaction supersedes all earlier versions.